VLSI program for ASIC and FPGA Design

Course Overview

Course Description This course provides professors with an introduction to designing with Xilinx FPGAs using ISE® Foundation™ software.
Level Introductory
Duration 60hrs
Who should attend? Student who are new to FPGAs or Xilinx technology and wish to use Xilinx All Programmable devices in digital design
Pre-requisites
  • Understanding Digital design experience
  • Basic HDL knowledge (VHDL or Verilog)
  • Understanding of 8-bit microcontrollers

Skills Gained

After completing this workshop, you will be able to:

  • Describe the general FPGA architectures and the design flow for ASIC and FPGA
  • Communicate design timing objectives through the use of global timing constraints
  • Pinpoint design bottlenecks using the reports
  • Utilize synthesis options to improve performance
  • Understand the various implementation options
  • Create and integrate IP cores into your design flow using CORE Generator™ software
  • Configure FPGA architecture features, such as DCM, using the Architecture Wizard

Course Outline Overview

FEATURES:
  • Basic FPGA Architecture
  • Xilinx Tool Flow
    • An introduction to FPGA design flow. Create project containing the design and simulate the design using the ISim HDL simulator provided with the ISE Foundation software.
  • Architecture Wizard and Pins Assignment
  • Use the Architecture Wizard to configure design. Assign pin locations with PACE. Implement design to generate a bitstream file.
  • Reading Reports
  • Global Timing Constraints
  • Enter and analyze the effects of global timing constraints. Download and test the design.
  • FPGA Design Techniques
  • Synchronous Design Techniques
  • Synthesis Techniques with Xilinx Synthesis Technology (XST)
    • Set various synthesis options to improve results for a design. Download the design.
  • Implementation Options

Module – 1

Digital Logic Design Fundamentals
  • COMBINATIONAL CKT
  • SEQUENTIAL CKT
VLSI Design flow methodology
  • XILINX ISE DESING FLOW
  • ISE SIMULATOR FOR SIMULATION
  • PROGRAMMING XILINX FPGA
PLD (ARCHICTECTURE)
  • CPLD
  • FPGA
  • XILINX FPGA

Module – 2

  • VHDL: - Language Fundamentals (entity, Architecture, Statements, Configuration).
  • Concurrent statements
  • Sequential statement (IF, FOR, LOOP, CASE FOR GENERATE).
  • Data Types, operators and attributes.
    • Gate level design
    • Data flow design
    • Behavioral design
    • Structural design
  • Modeling latches, flip-flops, multiplexers, address decoder
  • Designing shift register, counter, memory
  • State Machines (Definition types, examples and industry rules

Module – 3

  • Verilog - Language Fundamentals (Module).
  • Verilog HDL syntax
  • Data Types, operators and attributes.
    • Switch level desig
    • Gate level design
    • Data flow design
    • Behavioral design
    • Structural design
  • Modeling latches, flip-flops, multiplexers, address decoder
  • Designing shift register, counter, memory
  • Interfacing : LED, Switch, seven segment display

Module – 4

  • FPGA/CPLD: Hard ware configuration with Xilinx
  • Testing programmers developed earlier on FPGA/CPLD board